FIG. 21 shows a sectional view of a silicon carbide semiconductor device including a J-FET (junction type field-effect transistor) according to a prior art. The silicon carbide semiconductor device shown in FIG. 21 has a trench structure. Concretely, the semiconductor device includes an N+ layer J1 which is a drain region, an N−-type drift layer J2 which overlies the N+-type layer J1, an N+-type source layer J3 which overlies the N−-type drift layer J2, a P+-type layer J5 which is formed along the bottom surface of a trench J4 that is deep enough to penetrate through the N+-type source layer J3 and to arrive at the N−-type drift layer J2, a P+-type gate layer J6 which is formed along the side surface of the trench J4 and which communicates with the P+-type layer J5, an insulator film J7 which is formed on the side surface of the trench J4, a gate wiring line J8 which is electrically connected with the P+-type gate layer J6 through the P+-type layer J5, a silicon oxide film J9 which is formed within the trench J4, a source electrode J10 which is electrically connected with the source layer J3, and a drain electrode J11 which is electrically connected with the N+ layer J1 (refer to, for example, Non-patent Document 1; Zhao, J. H. et al: 3.6 mΩcm−2, 1726V 4H-SiC Normally-off Trenched-and-Implanted Vertical JFETs, “Power Semiconductor Device and ICs, 2003, Proceedings, ISPSD' 03. 2003 IEEE 15th International Symposium”, IEEE, 14-17 Apr. 2003, p. 50-53). Incidentally, a region J12 enclosed with a broken line is a region which chiefly functions as the J-FET.
With the silicon carbide semiconductor device, owing to the adoption of the trench structure, the integration degree of the J-FETs is easily raised by minimizing a cell size, and the ON-resistance of the semiconductor device can be lowered in accordance with the integration degree.
Besides, a silicon carbide semiconductor device of another structure is such that a MOSFET is included instead of the J-FET, and that a diode region formed with a diode is added between cell regions in each of which the transistor is configured (refer to, for example, JP-A-2005-108926). With the silicon carbide semiconductor device, the region which is not inherently formed in the cell region is added.
In the former of the silicon carbide semiconductor devices mentioned above, the P+-type layer J5 and the P+-type gate layer J6 are electrically connected with a gate electrode, and a P-type region connected to the source electrode as is included in a general MOSFET is not disposed, so that a diode connected to the source electrode is not built in structurally.
In order to perform an inverter operation with the silicon carbide semiconductor device, therefore, a chip formed with a diode for causing a back current, namely, a current reverse in sense to that of the J-FET to flow needs to be externally assembled to a chip formed with the J-FETs, or a diode region formed with a diode needs to be disposed in the same chip as the chip formed with the J-FETs.
In the case of the external assemblage, however, the two chips are connected by a wiring line, to incur the problems that a switching loss ascribable to the inductance of the wiring line occurs, and that a surge voltage increases. Therefore, it is better to build the diode in the silicon carbide semiconductor device of the above structure, than to externally mount the diode on the semiconductor device.
In this regard, when a method for forming the built-in diode is studied, the structure in which the diode region is added separately from the cell regions, in the same chip, is concretely considered as in JP-A-2005-108926.
From the viewpoints of facilitating the design of the layout of the chip and making the size of the chip smaller, however, a structure in which a diode region is formed by effectively utilizing part of the cell region is more favorable than the structure in which the diode region is added separately from the cell regions, within the chip.
Thus, it is required for a silicon carbide semiconductor device including a J-FET of trench structure, in which a diode is built in part of a cell region formed with the J-FET.